The objective of this material is to provide a simple introduction to digital design using Verilog; thus, many features of verilog itself are left uncovered.
Local resources on Verilog:
There is also an ALTERNATIVE manual by Dr Hyde of
University, Lewisburg PA
(note: VeriWell is not available at this Edinburgh site)
Books on Verilog and some Verilog related links
A special thanks goes to Cadence UK for donating a loan of multiple licences to create the Cadence Laboratory for Scotland at the Department of Electrical Engineering in the University of Edinburgh, Scotland, UK
While every attempt has been made to validate the information, errors may still exist; therefore, we offer no guarantees and we are grateful for any feedback on the material found herein.
Gerard M Blair was a Senior Lecturer in VLSI Design and Project Management in the Department of Electrical Engineering, The University of Edinburgh, Scotland UK. He welcomes feedback either by email email@example.com or by other methods found here